1. Field of the Invention
The present invention relates to the field of integrated circuits and, more specifically, of integrated circuits of very small dimensions, on the order of some ten nanometers.
2. Discussion of the Related Art
In the field of integrated circuits containing transistors having dimensions on the order of some ten nanometers, MOS transistors formed on a thin silicon layer are here considered. It has been acknowledged that the behavior of such transistors is different according to whether, when the transistor is on, the channel region takes up the entire thickness of a very thin silicon layer or takes up but a portion of the thickness of a slightly thicker silicon layer. In the first case, it is spoken of fully depleted transistors and, in the second case, of partially depleted transistors. For example, for a MOS transistor having a gate length on the order of 10 nm, a fully depleted transistor will be formed in a silicon layer of a thickness from 10 to 20 nm and the source and drain regions will take up this entire thickness. However, a partially depleted transistor will be, for example, formed in a silicon layer having a thickness of approximately 70 nm, the source and drain regions penetrating down to a depth ranging from approximately 10 to 20 nanometers.
It may be desired to form, in a same integrated circuit, fully depleted transistors which will have the advantage of a great switching speed and partially depleted transistors which will have the advantage of being able to stand slightly higher voltages than fully depleted transistors.